Dispositivos Lógicos Programáveis: mudanças entre as edições

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<syntaxhighlight lang="vhdl">
<syntaxhighlight lang="vhdl">
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors.  Please refer to the
-- applicable agreement for further details.


-- PROGRAM "Quartus II 32-bit"
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
-- CREATED "Fri May 12 14:23:31 2017"
-- CREATED "Fri May 12 15:17:16 2017"


LIBRARY ieee;
LIBRARY ieee;
Linha 26: Linha 12:
LIBRARY work;
LIBRARY work;


ENTITY portasAnd IS  
ENTITY portaE IS  
PORT
PORT
(
(
A :  IN  STD_LOGIC;
A :  IN  STD_LOGIC;
B :  IN  STD_LOGIC;
B :  IN  STD_LOGIC;
C :  IN  STD_LOGIC;
S :  OUT  STD_LOGIC
D :  IN  STD_LOGIC;
AB :  OUT  STD_LOGIC;
ABC :  OUT  STD_LOGIC;
ABCD :  OUT  STD_LOGIC
);
);
END portasAnd;
END portaE;
 
ARCHITECTURE bdf_type OF portasAnd IS
 
SIGNAL SYNTHESIZED_WIRE_0 :  STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 :  STD_LOGIC;


ARCHITECTURE bdf_type OF portaE IS


BEGIN  
BEGIN  
AB <= SYNTHESIZED_WIRE_0;
ABC <= SYNTHESIZED_WIRE_1;


S <= A AND B;


END bdf_type;


SYNTHESIZED_WIRE_0 <= A AND B;
SYNTHESIZED_WIRE_1 <= SYNTHESIZED_WIRE_0 AND C;
ABCD <= SYNTHESIZED_WIRE_1 AND D;
END bdf_type;
</syntaxhighlight>
</syntaxhighlight>


Edição das 18h18min de 12 de maio de 2017

Dispositivos Lógicos Programáveis

-- PROGRAM		"Quartus II 32-bit"
-- VERSION		"Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
-- CREATED		"Fri May 12 15:17:16 2017"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY portaE IS 
	PORT
	(
		A :  IN  STD_LOGIC;
		B :  IN  STD_LOGIC;
		S :  OUT  STD_LOGIC
	);
END portaE;

ARCHITECTURE bdf_type OF portaE IS 

BEGIN 

S <= A AND B;

END bdf_type;

--Evandro.cantu (discussão) 14h03min de 12 de maio de 2017 (BRT)

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